The present application relates generally to the field of semiconductor devices, and more particularly, to integrated circuits and methods for forming the integrated circuits.
Memory circuits have been used in various applications. Conventionally, memory circuits can include DRAM, SRAM, or non-volatile memory circuits such as ROM. The memory circuits typically include a plurality of memory cells arranged in arrays. The memory cells are typically accessed through a bit line (BL) (associated with a column of the array) and a word line (WL) (associated with a row of the array). The memory cell at the intersection of the specified BL and WL is the addressed cell. An exemplary SRAM memory cell is a 6-transistor (6-T) static memory cell. The 6-T SRAM memory cell is coupled with other cells in the array and peripheral circuitry using a bit line (BL), a complement bit line (bit line bar) (BLB), and a word line (WL). Four of the six transistors form two cross-coupled inverters for storing a datum representing “0” or “1”. The remaining two transistors serve as access transistors to control the access of the datum stored within the memory cell. Various other memory cell designs are also used in a variety of applications. Configuration of the memory cell, BL, and WL can affect performance and a suitable configuration for performance and spacing is desired.